Get 3D Nanoelectronic Computer Architecture and Implementation PDF

By D. Crawley, K. Nikolic, M. Forshaw

ISBN-10: 0750310030

ISBN-13: 9780750310031

It's turning into more and more transparent that the two-dimensional format of units on desktop chips is beginning to prevent the advance of high-performance desktops. three-d buildings can be had to give you the functionality required to enforce computationally in depth projects. three-D Nanoelectronic machine structure and Implementation stories the state-of-the-art in nanoelectronic machine layout and fabrication and discusses the architectural facets of three-D designs, together with the potential use of molecular wiring and carbon nanotube interconnections. it is a invaluable reference for these curious about the layout and improvement of nanoelectronic units and expertise.

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A possible solution would be to still use identical layers in the stack and only implement one-half of the PE logic in each layer. Connections between the two © IOP Publishing Ltd 2005 layers would enable a complete PE to be constructed. If a simple self-checking scheme could be implemented without a prohibitive increase in complexity, then a time-redundancy scheme might be used to achieve fault tolerance. For a real-time system, this might not be acceptable, however. An alternative would be not to use any explicit fault tolerance at all and simply rely on the inherent robustness of the array processor itself [19].

Also, because of their capacitive nature, the signal paths can only transmit ac signals so it is necessary to design and implement an appropriate signalling scheme. This could introduce problems of excessive power dissipation. Finally, an inductive signalling system has also been proposed [11] in which vertical signal transmission is implemented by means of metal spiral inductors. © IOP Publishing Ltd 2005 Essentially, the system consists of an array of air-cored transformers with one ‘winding’ on the lower chip and the other on the upper chip.

Plots to show the molecular wire conductivity σ that is needed to achieve a given data transmission bandwidth between a CMOS-driver–receiver combination, connected by a through-chip via and a molecular wire, as a function of the size of the connecting pad (assumed to be square). Molecular wire length = 5 µm. processors can be switched off to reduce the heating. Some alternative faulttolerant techniques for PE logic/memory are also examined in the next section, while chapter 12 discusses fault-tolerance techniques in more general terms.

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3D Nanoelectronic Computer Architecture and Implementation (Series in Materials Science and Engineering) by D. Crawley, K. Nikolic, M. Forshaw


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