By Ricardo Martins, Nuno Lourenço, Nuno Horta
This publication introduces readers to quite a few instruments for analog structure layout automation. After discussing the situation and routing challenge in digital layout automation (EDA), the authors review a number of computerized structure iteration instruments, in addition to the newest advances in analog layout-aware circuit sizing. The dialogue comprises diversified tools for automated placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The innovations and algorithms of all of the modules are completely defined, allowing readers to breed the methodologies, increase the standard in their designs, or use them as start line for a brand new instrument. the entire tools defined are utilized to sensible examples for a 130nm layout procedure, in addition to placement and routing benchmark sets.
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Extra info for Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques
However, the routing task of the proceeding is where the most of the difficulties remain. This is clear when observing the limitations of the current approaches, and the completely lack of routing automation in commercial EDA, only user-assisted functionalities. Furthermore, maintaining a model/template for routing proved to require huge setup time, and results in a setup that is application dependent, a maintenance effort beyond tolerable. For the routing approaches considering only wire planning or path assignment abstractly from the silicon level and technology-inherent design rules, simplistic ‘dotmodels’ are used to represent these complex multilayer multiport terminal structures.
In each iteration, the floorplan is exhaustively explored by enumeration using Plantage , and then the best placement, selected based on some performance criteria, is routed and considered for post-layout simulation. 3 Parasitic Extractors Used in Layout-Aware Approaches The parasitic structures extracted from the layout must be precise enough to guide the parasitic-aware circuit sizing in the right direction. In  a 1/2-D model is chosen but only applied for the area and fringing capacitance of the metal and poly stripes of the circuit’s critical nets, which makes the estimation quick, but loses accuracy and needs user intervention to identify the critical nets.
Integr. Circuits Syst. 517–522 16.
Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques by Ricardo Martins, Nuno Lourenço, Nuno Horta